The present invention relates to a reference current generator circuit that generates a reference current for generating a reference voltage, and particularly to a circuit configuration for performing an operation at a low voltage.
As an example of a reference voltage generator circuit for generating a reference voltage free of temperature dependence, there has heretofore been known one described in a patent document 1 (Japanese Unexamined Patent Publication No. 2003-131749).
The present patent document 1 has described a reference voltage generator circuit using a bandgap reference voltage circuit, which reduces a through current by reliably starting up at power-on and reduces power consumption by the reduction in the through current.
As examples of reference current generator circuits for generating reference voltages, there have been known ones described in, for example, a patent document 2 (Japanese Unexamined Patent Publication No. 2000-75947) and a non-patent document 1 (Hironori Banda, Hitoshi Shiga, Akira Umezawa, Takeshi Miyaba, Toru Tanzawa, Shigeru Atsumi and Koji Sakui, “A CMOS Bandgap Reference Circuit with Sub-1-V Operation”, fifth edition, Vol. No. 34 (U.S.A), IEEE Journal of Solid-State Circuits, May 1999, p. 670-674).
FIG. 2 is a schematic circuit diagram showing a configuration example of the conventional reference current generator circuit described in each of the patent document 1 and the non-patent document 1 or the like.
The reference current generator circuit is inputted with a source voltage Vcc and comprises a current generating circuit section or part 10, a differential amplifying circuit section or part 20 which generates a control voltage from a forward voltage Vd and a voltage Vt, and an output circuit section or part 30 which converts a reference current Iref into a reference voltage Vref and outputs it therefrom.
In the current generating circuit part 10, an enhancement P channel type MOS transistor (hereinafter called “PMOS”) 11 and a diode 12 are connected in series between a source voltage terminal VCC and a ground terminal GND. And a resistor 13 is connected in parallel with the diode 12 via an output node VD. Further, a PMOS 14, a resistor 15 and a diode circuit section or part 16 are connected in series between the source voltage terminal VCC and the ground terminal GND. And a resistor 17 is connected in parallel with the series-connected resistor 15 and diode circuit part 16 via an output node VT. The diode circuit part 16 comprises n diodes 16aconnected in parallel.
The differential amplifying circuit part 20 has a differential amplifying circuit 21 provided between the source voltage terminal VCC and the ground terminal GND, which is connected to the output nodes VD and VT and outputs a control voltage Vc to the gates of the PMOSs 11 and 14. Further, a PMOS 22 of which the gate is inputted with a control voltage Vc, and a diode-connected enhancement N channel type MOS transistor (hereinafter called “NMOS”) 23 are connected in series between the source voltage terminal VCC and the ground terminal GND. A capacitor 24 for stable operation is connected to its corresponding input terminal of the differential amplifying circuit 21 connected to the output node VD.
The differential amplifying circuit 21 has a current mirror circuit constituted of PMOSs 21a and 21b, a depletion N channel type MOS transistor (hereinafter called “DNMOS”) 21c connected to the output node VT and the PMOS 21b, a DNMOS 21d which is connected to the output node VD and the PMOS 21b and outputs the control voltage Vc, and an NMOS 21e which is connected between the DNMOSs 21c and 21d and the ground terminal GND and constitutes a current mirror circuit together with the NMOS 23.
The output circuit part 30 includes a capacitor 31 for stable operation provided between the source voltage terminal VCC and the collector of the DNMOS 21d corresponding to an output terminal of the differential amplifying circuit 21, a PMOS 32 which is inputted with the control voltage Vc and thereby causes a reference current Iref to flow, an NMOS 33 which forcedly short-circuits the gates of the PMOSs 11, 14, 22 and 32 with the ground terminal GND when a control signal PONRST is in an on state, and a resistor 34 which converts the reference current Iref to a reference voltage Vref.
The operation of the conventional reference current generator circuit shown in FIG. 2 will next be explained.
A forward voltage Vd outputted from the output node VD and a voltage Vt outputted from the output node VT are inputted. In doing so, the differential amplifying circuit part 20 is operated so as to keep the forward voltage Vd and the voltage Vt at the same potential by an imaginary short circuit.
Since the forward voltage Vd and the voltage Vt are of the same potential, a source voltage Vcc is commonly applied to the sources of the PMOSs 11, 14 and 32, and a control voltage is commonly applied to the gates thereof. Assume that the sizes of channel widths W and channel lengths L of the PMOSs 11, 14 and 32 are identical and they are respectively being operated in a saturated region. When currents that flow through the PMOS 11, PMOS 14 and PMOS 32 are respectively defined as Ids11, Ids14 and Ids32, the currents Ids11, Ids14 and Ids32 become equal to one another.
Assuming now that the resistance value of the resistor 13 is R13, the resistance value of the resistor 17 is R17 and the resistance values R13 and R17 are exactly the same, the forward voltage Vd=Vt, the current Ids11=Ids14 and the resistance value R13=R17 are established. Therefore, the currents that flow through the resistors 13 and 17 become equal to each other, and the currents that flow through the diode 12 and the diode circuit part 16 become also identical to each other. Assuming that the current that flows through each of the diode 12 and the diode circuit part 16, is defined as Ids1, the Boltzmann constant is defined K, the ambient temperature is defined as T, the electric charge is defined as q, and the saturation current of the diode 12 is defined as Is, a voltage Vd12 applied to the diode 12 can be expressed in the following equation:Vd12=KT/q×LN(Ids1/Is)   (1)
Since the number of the diodes 16a connected in parallel is n, a current ratio flowing through each diode, per diode becomes 1:1/n. Thus, a voltage Vd16 applied to the diode circuit part 16 can be expressed in the following equation:Vd16=KT/q×LN(Ids1/n×Is)   (2)
Further, a voltage V15 applied across the resistor 15 can be expressed in the following equation:V15=Vd12−Vd16=KT/q×LN(n)   (3)
Assuming that the resistance value of the resistor 15 is R15, the voltage applied across the resistor 15 is V15, and the current flowing through the resistor 15 at this time is Ids1, the current Ids1 can be expressed in the following equation:Ids1=V15/R15=(1/R15)×KT/q×LN(n)   (4)
Assume now that the current flowing through the resistor 17 is Ids2. Since the voltages Vd12=Vd16 and the resistance values R13=R17, the current Ids2 can be expressed in the following equation:
                                                                        Ids                ⁢                                                                  ⁢                2                            =                              Vd                ⁢                                                                  ⁢                                  16                  /                  R                                ⁢                                                                  ⁢                17                                                                                        =                              Vd                ⁢                                                                  ⁢                                  12                  /                  R                                ⁢                                                                  ⁢                13                                                                                        =                                                (                                                            1                      /                      R                                        ⁢                                                                                  ⁢                    13                                    )                                ×                                  KT                  /                  q                                ×                                  LN                  ⁡                                      (                                          Ids                      ⁢                                                                                          ⁢                                              1                        /                        Is                                                              )                                                                                                          (        5        )            
Thus, currents Ids11, 14 and 32 can be expressed in the following equation:Ids11=Ids14=Ids32=Ids1+Ids2
Assuming that the resistance value of the resistor 34 is R34, a reference voltage Vref can be expressed in the following equation in accordance with the equation (5):
                                                        Vref              =                              R                ⁢                                                                  ⁢                34                ×                                  (                                      Ids                    ⁢                                                                                  ⁢                    32                                    )                                                                                                        =                              R                ⁢                                                                  ⁢                34                ×                                  (                                                            Ids                      ⁢                                                                                          ⁢                      1                                        +                                          Ids                      ⁢                                                                                          ⁢                      2                                                        )                                                                                                        =                                                (                                      R                    ⁢                                                                                  ⁢                                          34                      /                      R                                        ⁢                                                                                  ⁢                    13                                    )                                ×                                  [                                                                                                                                          Vd                            ⁢                                                                                                                  ⁢                            12                                                    +                                                      R                            ⁢                                                                                                                  ⁢                                                          13                              /                              R                                                        ⁢                                                                                                                  ⁢                            15                            ×                                                                                                                                                                                                                    KT                            /                            q                                                    ×                                                      LN                            ⁡                                                          (                              n                              )                                                                                                                                                            ]                                                                                        (        6        )            
Thus, the conventional reference current generator circuit generates the reference current Iref by the PMOS 32 and allows the reference current Iref to flow through the load resistor 34 connected to the PMOS 32, thereby generating a constant reference voltage Vref free of temperature dependence from a reference voltage output terminal VREF.
However, the conventional reference current generator circuit was accompanied by such problems as described in the following (a) through (c).
(a) The equation (6) is not established unless R13=R17. That is, the conventional reference current generator circuit is of a circuit affected by variations in the production of the resistors 13 and 17.
(b) The PMOSs 11, 14 and 32 respectively need to be operated in the saturated region. Further, since the forward voltage Vd and the voltage Vt are determined depending upon diode characteristics, it is difficult to attain a reduction in voltage.
(c) In order to attain the voltage reduction, the channel widths W and channel lengths L of the PMOSs 11, 14 and 32, and the sizes of the diodes 12 and 16a are enlarged and the amounts of current are increased, whereby their operating voltages are reduced. However, demerits like an increase in chip size and an increase in current consumption occur. Since the characteristics of the PMOSs 11, 14 and 32 are determined depending on the process as the case may be, it is difficult to attain the reduction in voltage by circuit design.